Quatech 802.11B/G Manual de usuario descargar pdf (Pagina 21)

Airborne Enterprise Module Databook Quatech, Inc.

100-8080-120 7/15/2010 21

7.0 SPI Interface

The following section details the SPI interface specification for both hardware timing and

SPI protocol. The device is a SPI slave and requires a compatible SPI master for

operation.

7.1 Pinout

When the SPI interface is enabled, through the CLI or web interface, the

following pins are assigned for communication.

Table 10 - SPI Pinout Details

Pin Definition

SPI

UART2 Pin

Debug

Master In Slave Out (MISO)

Master Out Slave In (MOSI)

SPI Interrupt (SPI_INT)

SPI Clock (SPI_CLK)

SPI Select (/SPI_SEL)

Data In (RxD2, DTXD)

Data out (TxD2, DRXD)

Ready-to-Send (RTS2)

Clear-to-Send (CTS2)

Table 11 - SPI Signal Descriptions

Pin Definition

Description

Master In Slave Out (MISO)

Serial Data OUT; must be connected to the serial data in of

the master.

Master Out Slave In (MOSI)

Serial Data IN; Must be connected to the serial data out of the

master.

SPI Interrupt (SPI_INT)

Interrupt signal driver by slave see Table 15 for details of

operation.

SPI Clock (SPI_CLK)

SPI clock sourced from the master.

SPI Select (/SPI_SEL)

Enable the SPI slave, sourced from the master. Active low

signal.

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Quatech 802.11B/G Manual de usuario Pagina 21