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2 – Airborne Wireless LAN Node Module

Page 12 Airborne Wireless LAN Node Module Data Book 100-8004-102G

Quatech, Inc. Confidential

2.5 HOST PIN ASSIGNMENTS AND SIGNAL DESCRIPTIONS

The interconnect between the Module and the Host system is a 4 mm high, 36-pin, Hirose

DF12-36DS-0.5 V(80) connector.

The part number for the 4-mm high mating connector to be mounted on the PCB is the Hirose

DF12-36DP-0.5 V(80). Table 3 lists the Module’s Host pin assignments.

Table 3. Airborne WLN Module Pin Assignments

Pin Signal Sink Source Description

1 GND Ground

2 TSI ISP Serial Data In (see Note 1)

3 DV

Power, +3.3 V

4 DV

Power, +3.3 V

5 V2.5 2.5 V Reference output (for reference only)

6 RFU Reserved (see Note 1)

7 /RESET Reset – active low. A transition to high releases the reset condition

(see “Reset” on page 16). There is a weak pull-up on this pin, but

floating this pin does not guarantee a logic high.

8 /TSS ISP Slave Select (active low) (see Note 1)

9 G6 4 mA 4 mA Used as analog input or digital output (see Table 6). Provides 3.3 V

CMOS-compatible digital output (V

≤0.4, 2.4 V≤ V

10 TSO ISP Serial Data Out (see Note 1)

11 G3 4 mA 4 mA Used as analog input or digital output (see Table 6). Provides 3.3 V

CMOS-compatible digital output (V

≤0.4, 2.4 V≤ V

Port can be used at bootup to reset the Module to factory defaults –

see Section 2.8.2, Factory Restart on page 19 for more information.

12 F5 8 mA 8 mA Used as high-speed UART or high-speed SPI Slave (see Table 5).

Signal is TTL-compatible and 5 V tolerant.

13 G5 4 mA 4 mA Used as analog input or digital output (see Table 6). Provides 3.3 V

CMOS-compatible digital output (V

≤0.4, 2.4 V≤ V

14 G4 4 mA 4 mA Used as analog input or digital output (see Table 6). Provides 3.3 V

CMOS-compatible digital output (V

≤0.4, 2.4 V≤ V

Ground

17 G2 4 mA 4 mA Used as analog input or digital output (see Table 6). Provides 3.3 V

CMOS-compatible digital output (V

≤0.4, 2.4 V≤ V

18 F4 8 mA 8 mA Used as high-speed UART or high-speed SPI Slave (see Table 5).

Signal is TTL-compatible and 5 V tolerant.

19 G1 4 mA 4 mA Used as analog input or digital output (see Table 6). Provides 3.3 V

CMOS-compatible digital output (V

≤0.4, 2.4 V≤ V

20 TSCK ISP Serial Clock (see Note 1)

1 2 ... 13 14 15 16 17 18 19 20 21 22 23 ... 66 67

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