
2 – Airborne Wireless LAN Node Module
100-8004-102G Airborne Wireless LAN Node Module Data Book
Page 13
Quatech, Inc. Confidential
Table 3. Airborne WLN Module Pin Assignments
Pin Signal Sink Source Description
21 G7 4 mA 4 mA Used as analog input or digital output (see Table 6). Provides 3.3 V
CMOS-compatible digital output (V
OL
≤0.4, 2.4 V≤ V
OH
).
22 G0 4 mA 4 mA
UART: Used as analog input or digital output (see Table 6). Provides
3.3 V CMOS-compatible digital output (V
OL
≤0.4, 2.4 V≤ V
OH
).
SPI: Used as system interrupt (see Table 5).
Signal is 3.3 V TTL-compatible and 5 V tolerant.
23 F6 8 mA 8 mA Used for digital I/O and Status (see Table 4). Pre-configured as a
digital output in firmware and represents the CONNECT status.
24 F7 8 mA 8 mA Used as high-speed UART or high-speed SPI Slave (see Table 5).
Signal is 3.3 V TTL-compatible and 5 V tolerant.
25 F0 8 mA 8 mA Used for digital I/O and status (see Table 4). Pre-configured as a
digital output in firmware and represents the POST status.
26 F3 8 mA 8 mA Used for digital I/O and status (see Table 4). Pre-configured as a
digital output in firmware and represents the WLAN CFG status.
27 F2 24 mA 24 mA Used for digital I/O and status (see Table 4). Pre-configured as a
digital output in firmware and represents the RF LINK status.
28 F1 24 mA 24 mA Used as high-speed UART or high-speed SPI Slave (see Table 5).
Signal is TTL-compatible and 5 V tolerant.
29 E6 24 mA 24 mA General Purpose Digital I/O, 5 V tolerant.
30 E5 24 mA 24 mA General Purpose Digital I/O, 5 V tolerant
31 E7 8 mA 8 mA General Purpose Digital I/O, 5 V tolerant.
32 E4 8 mA 8 mA General Purpose Digital I/O, 5 V tolerant.
33 DV
DD
Power, +3.3 V
34 DV
DD
Power, +3.3 V
35 /RF_LED 2 mA RF Status output, active low, represents RADIO ACTIVITY
(see Table 4)
36 V
SS
Ground
Note 1: The ISP pins are tied high internally. ISP pins are reserved for factory based firmware loading.
ISP = in-system programming port
V
OL
= low-output voltage
V
OH
= high-output voltage
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