Quatech 802.11B/G Especificaciones descargar pdf (Pagina 26)

2 – Airborne Wireless LAN Node Module

Page 20 Airborne Wireless LAN Node Module Data Book 100-8004-102G

Quatech, Inc. Confidential

2.9 DESIGN GUIDELINES

2.9.1 General Design Guidelines

The Module is designed to be implemented into a variety of applications. Any design must meet

the following guidelines:

 Provide 3.3 V to all DV

power pins.

 Provide ground connections to all V

pins.

 Tie port G3 to the Module’s 2.5 V V

ref

through a 10 KΩ resistor to prevent the Module

from resetting itself to factory defaults at startup.

 Tie all unused I/O to ground via 10 KΩ resistors. If the state of the I/O can be controlled,

set all unused I/O as outputs.

 Do not exceed 2.5 V on any port G pins configured as analog inputs.

 Provide a connection to a suitable antenna.

 TSI, TSS, TSO, TSCK, and RFU should be left as No Connects (they are pulled up

internally).

 Carefully follow the Hirose DF12 connector placement, mounting, and precautions for

use to avoid shorts due to an incorrect soldering profile.

2.9.2 SPI Design Guidelines

The Module with the SPI interface is designed to be implemented into a variety of applications.

Any design must meet the following guidelines:

 Data transfer from master to slave is carried out across the MOSI (Master-Out/Slave-In)

line.

 Data transfer from slave to master is carried out across the MISO (Master-In/Slave-Out)

line.

 All data transfers are synchronized by the Master’s serial clock (SCK). One bit of data is

transferred every clock pulse, and one octet can be exchanged in eight (8) clock cycles.

 Communication is enabled when the /SS (Slave Select) line is pulled low.

 An Interrupt Master (INT) line is used by the Slave to signal the Master that data is

available.

 This protocol is completely octet (8 bits) aligned.

 A frame is defined as those octets that are bounded by the Slave Select assertion (from

the time /SS goes low, until it returns high). SPI requires that commands be framed, so a

frame can be of varying sizes, especially for the read and write command sequences.

This puts a timing strain on the system to quickly deal with the data. With the SCK

running at 2MHz, the system has 4 microseconds to deal with an octet transferred (read

or write) between the driver and the buffer.

 If a frame is prematurely terminated (before the octet count is completed), the driver

must ensure that the data is properly accounted for and the pointers managed with the

actual number of octets transferred, not the number of initially defined.

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Quatech 802.11B/G Especificaciones Pagina 26

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