Quatech 802.11B/G Especificaciones descargar pdf (Pagina 23)

2 – Airborne Wireless LAN Node Module

100-8004-102G Airborne Wireless LAN Node Module Data Book

Page 17

Quatech, Inc. Confidential

Figure 3. Power-up Sequence (Separate /RESET Signal)

Figure 4 shows the on-chip POR sequence in which the /RESET and DV

pins are tied

together. The DV

signal is stable before the startup timer expires. In this case, the CPU

receives a reliable reset.

Figure 4. Power-up Sequence (/RESET Tied to DV

)

Figure 5 shows a situation where DV

rises too slowly. In this scenario, the startup timer times-

out before DV

reaches a valid operating voltage level (DV

min). As a result, the CPU comes

out of reset and starts operating with the supply voltage below the level required for reliable

performance. In this situation, an external RC circuit is recommended for driving /RESET. The

RC delay should exceed five times the time period required for DV

to reach a valid operating

voltage.

Figure 5. DV

Rise Time Exceeds Tstartup

Figure 6 shows the recommended external reset circuit. The external reset circuit is required

only if the DV

rise time has the possibility of being too slow (refer to Table 11 on page 25).

/RESET

POR

Startup Time

(Timeout)

Internal

Reset Signal

/RESET

POR

Startup Timer

(Timeout)

Internal

Reset Signal

/RESET

POR

Startup Time

(Timeout)

Internal

Reset Signal

WUDX

70ns

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Quatech 802.11B/G Especificaciones Pagina 23

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