Quatech 802.11B/G Especificaciones descargar pdf (Pagina 22)

2 – Airborne Wireless LAN Node Module

Page 16 Airborne Wireless LAN Node Module Data Book 100-8004-102G

Quatech, Inc. Confidential

2.6 ANTENNA PIN ASSIGNMENTS AND DESCRIPTIONS

Figure 2 shows the Module antenna connectors and Table 8 describes their pin assignments.

J2 is used for single-antenna operation. To implement antenna diversity, use both J1 and J2.

Table 8. Airborne WLN Module Antenna

Pin Assignments

Pin Description

J1 (left connector) Antenna 1 - Secondary

J2 (right connector) Antenna 2 - Primary

Figure 2. Antenna Connectors

2.7 RESET

The Module incorporates a Power-On Reset (POR) detector that generates an internal reset as

rises during power-up. An internal startup timer, together with a reset latch, controls the

reset timeout delay. On power-up, the reset latch is cleared (CPU held in reset), and the startup

timer starts counting when it detects a valid logic high signal on the /RESET pin (pin 7). When

the startup timer reaches the end of the timeout period, the reset latch is cleared, releasing the

CPU from reset.

Note:

CPU operation does not start until the CPU is released from reset and valid

core clocks are received past the system clock suspend circuit. The

Module’s POR is set to 1 millisecond.

Figure 3 shows a power-up sequence in which /RESET is not tied to the DV

pin, and the DV

signal is allowed to rise and stabilize before the /RESET pin is brought high. WUDX specifies

the length of time from the rising edge of /RESET until the device leaves reset. For the Module,

this length of time is set to 1 millisecond. In this case, the CPU receives a reliable reset.

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